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1)
March, 24th,
25th and 26th
·
Folder
of the event
·
News
at PAD site
·
News at IEEE
I Workshop
on OpenSPARC Architecture (USP, Brazil)
Introduction to Chip
Multithreaded and FPGA Implementation
This workshop will present about OpenSPARC Architecture, Details of OpenSPARC
Microarchitecture, Simulators for Chip Multithreaded (CMT), Performance
Modeling Tools, and Tools. The main goal is FPGA Implementation on OpenSPARC
T1.
OpenSPARC Specification
and FPGA Implementation (March, 24th,
25th and 26th )
Held at the
- Anfiteatro Engenharia Elétrica – USP
- Av. Professor Luciano Gualberto, Trav3 158
- Cidade Universitária. São Paulo – SP
- Hosted by Grupo de Computação Pervasiva e Alto Desempenho
(PAD/LSI) at Universidade de São Paulo – USP
  
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Monday
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March 24th,
2008
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8:30 – 9:00
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Continental
BreakfastRegistration
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Anfiteatro Engenharia
Elétrica
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9:00 – 9:15
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Welcome and
Introduction
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Sergio
T. Kofuji, USP and Eduardo Lima, SUN
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9:15
– 9:45
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Carlos
Thomaz, SUN
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OpenSPARC Community
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9:45
– 10:15
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Sergio
Kofuji, USP
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OpenSPARC
Program at USP
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10:15
– 10:45
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Sergio
Kofuji, USP
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Architectural Concepts:
Chip Multithreaded (CMT) Era
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10:45
– 11:15
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Coffee
Break
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11:15
– 11:45
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Sergio
Kofuji, USP
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Fine-Grained and
Course-Grained Applications for CMT
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11:45
– 12:15
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Sergio
Kofuji, USP
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SPARC
Architectures Generations
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12:15
– 12:45
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Sergio
Kofuji, USP
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Design Decisions
(Bandwidth, cache system, power)
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12:45
– 1:45
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Lunch
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1:45
– 2:15
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Sergio
Kofuji, USP
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OpenSPARC
T1 Microarchitecture
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2:15
– 2:45
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Sergio
Kofuji, USP
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FPGA Implementation on
OpenSPARC T1(video)Community Innovation Awards Contest
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2:45
– 3:15
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Sergio
Kofuji, USP
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Open Discussion
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3:15
– 3:45
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Coffee
Break
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3:45
– 4:15
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Sergio
Kofuji, USP
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OpenSPARC
T2 Microarchitecture
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4:15
– 5:15
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Sergio
Kofuji, USP
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Open
Discussion
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Tuesday
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March
25th, 2008
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8:30
– 9:00
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Opennning
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C1-10
Engenharia Elétrica
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9:00
– 9:15
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Welcome and
Introduction to Simulators for OpenSPARC T1
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Sergio Kofuji, USP and
Fernando Muzzi, LSI/Design House and Jussara Kofuji, PAD/USP
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9:15
– 9:45
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Fernando
Muzzi, LSI/USP
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Overview of SPARC
Architectural Model (SAM)
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9:45
– 10:15
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Fernando
Muzzi, LSI/USP
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Modeling Components
(Pipe, TLBs, ASICs)
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10:15
– 10:45
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Fernando
Muzzi, LSI/USP
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Modeling
of Device Drivers
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10:45
– 11:15
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Coffee
Break
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11:15
– 11:45
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Jussara
Kofuji, PAD/USP
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Introduction of SPARC
architectural Model (SAM) for OpenSPARC T2
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11:45
– 12:15
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Jussara
Kofuji, PAD/USP
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Legion – Fast
instruction accurate simulator for software developers
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12:15
– 12:45
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Jussara
Kofuji, PAD/USP
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RST
Trace Tool
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12:45
– 1:45
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Lunch
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1:45
– 2:15
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Introduction
to FPGA Implementation
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Sergio Kofuji, USP and
Edson Horta, Visiting Professor USP
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2:15
– 2:45
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Edson
Horta, USP
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Programmable
Logic Devices
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2:45
– 3:15
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Edson
Horta, USP
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ISE
Design Tool
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3:15
– 3:45
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Coffee
Break
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3:45
– 4:15
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Edson
Horta, USP
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Embedded
Processing in FPGA
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4:15
– 5:15
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Edson
Horta, USP
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EDK
Design Tool
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6:30
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Dinner
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Paulista
Grill’s restaurant
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Thursday
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March
26th, 2008
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8:30
– 9:00
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Opennning
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C1-10
Engenharia Elétrica
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9:00
– 9:15
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Introduction
to ModelSim
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German
Santos, DrEE USP
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9:15
– 9:45
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Stelvio
Barbosa, PAD/USP
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Lab
ModelSim
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9:45
– 10:15
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Renato
Machado, PAD/USP
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Lab
ModelSim
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10:15
– 10:45
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Open
Discussion
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German
Santos
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10:45
– 11:15
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Coffee
Break
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11:15
– 11:45
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Antonio
Amorim, PAD/USP
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Introduction
to Multicore Architectures
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11:45
– 12:15
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Jussara
Kofuji, PAD/USP
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Multicore
Programming Models
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12:15
– 12:45
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Antonio
Amorim, PAD/USP
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Paradigms of Multicore
Programming (overview of software development)
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12:45
– 1:45
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Lunch
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- Registration and informations: Please send
email to Jussara at pad.lsi.usp.br
- Cost Workshop: R$30,00 (Included Coffee
Break and Full registration)
- Dinner (Not included)
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